Power diodes based on monocrystalline silicon crystals allow only a limited current load. The temperature resistance of silicon diodes is restricted, and the function of a silicon power diode changes to a permanently connected resistance at temperatures above 200° C. Since the heat dissipation measures for semiconductor power modules cannot be improved indefinitely, there is a need to increasingly replace silicon power diodes by high-temperature-resistant SiC power diodes in semiconductor power modules.
In order to increase the current-carrying capacity of SiC power diodes such as this, it is necessary to enlarge the chip areas of the corresponding semiconductor power components. However, with enlargement of the chip areas, particularly in the case of SiC crystals, the respective defect density leads to a reduced yield and thus to a higher failure rate for large-area, SiC-based power semiconductor components. By way of example, the yield of SiC monocrystalline pieces falls from 89% for a chip area of 1 mm2 to 62% when the semiconductor chip area is tripled. This is associated with the disadvantage that large-area SiC power diode chips are subject to a failure risk which is more than 10% greater.
A further disadvantage of conventional power semiconductor modules is that the power semiconductor chips and the SiC power diodes are eutectically soldered by their rear-face metallization to corresponding metal layers on a power semiconductor component housing. At the high permissible operating temperatures of SiC diodes, there is a risk of eutectic soldered joints such as these on the rear faces of the SiC diodes melting once again, so that it is not possible to guarantee the reliability of high-power components such as these.
Furthermore, the eutectic melt requires a melt pool or melt area on the metal coating of the power semiconductor component housing which is larger than the rear face, to be applied to the metal coating, of the respective power semiconductor component. This has the disadvantage that considerably larger areas must be provided for the metal layer than the total area of the rear faces of the semiconductor power chip to be arranged in a semiconductor power module.